PERSONAL RESUME
Michael C. Kavcak
1505 Visalia Lane
Austin, TX 78727
Home Phone: (512) 835-9695
Email: sarge@kavcak.com
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Job Objective:
To obtain a leadership engineering position
Work Experience:
4/07 to 1/08
Verification Manager, Coherent Logix, Austin, TX
Responsible for all chip level verification. Put together a unit level testbench
for one of the blocks and found several bugs in silicon shortly after arriving. Put
together next generation chip level testbench, along with instruction generator.
Used Specman and SystemVerilog verification languages.
6/06 to 8/06
Consultant, Boeing, Los Angeles, CA
Assisted with verification of several FPGAs. Primary responsibilities included
helping to improve the current Specman verification environment, building a
new, faster Specman testbench for certain scenarios, writing tests and checks,
and giving direction on Specman and verification methodology.
8/05 to 12/05
Contract Engineer, Volt Technical Services, Austin, TX
AMD
Assisted the customer support division with the verification of a 3rd party ASIC
using Specman. Duties include evaluating current test plan, adding to the
current test environment, inserting coverage, and writing new tests.
9/04 to 3/05
Contract Engineer, Volt Technical Services, Austin, TX
Toshiba Cosimulation Team
Co-lead of a verification team made up of STI (Sony, Toshiba, IBM) employees
and contractors who are responsible for integrating and simulating the Cell
chip's interaction with other ASICs.
10/01 to 7/04
Design Manager, SMSC, Austin, TX
Responsible for all verification at Austin design center. Recent projects
include leading a team of engineers in the verification of a USB 2.0
hub using Specman and the Verisity USB eVC, as well as charting future
direction for the company and design center.
1/01 to 10/01
President, Sarge's Invincible Consulting, Austin, TX
Self-employed contractor available for all facets of ASIC and/or micro-
processor design, primarily working as a trainer for the Specman verification
product from Verisity.
9/00 to 12/00:
Macintosh Development Manager, 3dfx Interactive, Austin, TX
Responsible for coordinating the engineering effort behind 3dfx's
Macintosh products. Duties included organizing driver releases, interfacing
with numerous other groups in 3dfx and Apple, and effectively understanding
the 3dfx and Macintosh architectures.
2/00 to 9/00:
Senior Engineering Consultant, Qualis Design Corporation, Austin, TX
Team with ASIC design corporations to resolve all issues regarding the
designs from architecture to verification. Duties also included learning new
verification languages (Vera, Specman), and teaching classes in Verilog and
Specman.
8/96 to 11/99:
PowerPC Architect, Apple Computer, Austin, TX
Architecture and Performance Group
- Responsible for system and processor architecture phases of numerous
Power Macintosh computers. Duties include system modeling, performance
evaluation, application analysis, and new product/processor definition.
- Responsible for lab debug phase of next generation PowerPC processors and
systems. Duties include BootROM modifications, OpenFirmware coding, use of
PowerPC JTAG debug tool, and general new silicon/system troubleshooting.
- Liaison between Apple and Motorola for all issues concerning the processors.
Duties include communicating errata, conveying architecture details, and
answering processor/system specific questions for both companies.
3/93 to 7/96:
Product Development Engineer, AMD, Austin, TX
K7 design team
Responsible for all facets of design for integer core of next generation X86
microprocessor including architecture, RTL, logic design, circuit design,
timing analysis, verification, and compatibility.
SLE486 design team
Responsible for verification effort of SLE486. Duties included developing,
verifying, and maintaining a test suite. Other duties included making design
changes as necessary, and overseeing a group of contractors to assist in
verification.
486FPU design team
Responsible for logic and circuit design of several datapath blocks in 486FPU.
Later duties included assisting in design of integer/fpu interface, and leading
verification and debug effort.
1/92 to 1/93:
Contract Engineer, TAD Technical Services, Austin, TX
IBM 601 PowerPC design team
Responsible for simulating bus protocol on 601 PowerPC. Duties included
making behavioral level bus models and writing test cases to simulate the 601
PowerPC bus.
6/91 to 9/91:
Contract Engineer, TAD Technical Services, Austin, TX
AMD SONIC design team
Responsible for porting AMD 8051 microcontroller design into SONIC chip.
Duties included logic design and verification of microcontroller using
Quicksim and Verilog.
5/90 to 8/90:
Programmer, IBM, Research Triangle Park, NC
IBM LAN test team
Responsible for developing the initial parts of a program to perform
exhaustive testing on IBM token ring networks. Used a modular design for
program so that further additions would be easy to implement.
5/89 to 8/89:
Programmer, IBM, Research Triangle Park, NC
IBM LAN test team
Responsible for developing a test program which would operate across a
token ring remote bridge. Designed program to test bandwidth across the
bridge.
Education:
University of Texas at Austin, Austin, TX, 78712
Master's Degree Program: Electrical Engineering
Thesis: Controller for Associative Memory
Graduated: May, 1992 G.P.A. 3.43
Pennsylvania State University, University Park, PA, 16802
Graduated with distinction, B.S. degree: May, 1990
Major: Computer Engineering
Cumulative G.P.A. 3.55 Major G.P.A. 3.60
Activities:
- Men's Austin Baseball League
- Handy Wheels volunteer
- Holy Family School Standards Committee
- City of Austin flag football
- Penn State Club of Central Texas
- Hands on Housing
References:
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